FPGA BASED BOARD DESIGN SERVICES FOR MEMORY DEVICE CHARACTERIZATION BOARD
ID: 1333ND25QNB030052Type: Combined Synopsis/Solicitation
Overview

Buyer

COMMERCE, DEPARTMENT OFNATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGYDEPT OF COMMERCE NISTGAITHERSBURG, MD, 20899, USA

NAICS

Computer Systems Design Services (541512)

PSC

IT AND TELECOM - BUSINESS APPLICATION/APPLICATION DEVELOPMENT SUPPORT SERVICES (LABOR) (DA01)

Set Aside

Total Small Business Set-Aside (FAR 19.5) (SBA)
Timeline
  1. 1
    Posted Mar 13, 2025, 12:00 AM UTC
  2. 2
    Updated Apr 3, 2025, 12:00 AM UTC
  3. 3
    Due Apr 4, 2025, 9:00 PM UTC
Description

The Department of Commerce, specifically the National Institute of Standards and Technology (NIST), is seeking qualified small businesses to provide FPGA-based board design services for a memory device characterization board. The project involves the design, fabrication, and assembly of a custom memory characterization platform that integrates various components, including Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs), to facilitate the evaluation of advanced memory devices. This initiative is crucial for advancing research and industrial applications in memory technology, ensuring high standards in design and performance testing. Interested vendors must submit their firm-fixed-price quotations electronically by 5 PM EDT on April 4, 2025, and can direct inquiries to primary contact Joni L. Laster at joni.laster@nist.gov or secondary contact Forest Crumpler at forest.crumpler@nist.gov.

Point(s) of Contact
Files
Title
Posted
Apr 3, 2025, 11:04 AM UTC
The document is a combined synopsis/solicitation for FPGA-based board design services for memory device characterization by the National Institute of Standards and Technology (NIST). It is a Request for Quotation (RFQ) aimed at small businesses and follows simplified acquisition procedures under FAR guidelines. The contract involves designing, fabricating, and assembling a memory characterization platform featuring a custom memory array chip, ADCs, DACs, and necessary components for communication interfaces, intended for research and industrial use. Offerors are required to submit a firm-fixed-price quotation and demonstrate technical capability by detailing their design and fabrication experience, past performance on similar projects, and compliance with proposal instructions. The submission includes several volumes: technical proposal, experience documentation, past performance references, price quotation, and terms and conditions. Quotations must be received electronically by the specified deadline, and the evaluation will consider technical capability, experience, past performance, and price, with non-price factors being more significant. The RFQ emphasizes compliance with federal regulations, including the unique entity identifier registration and various federal acquisition clauses, ensuring alignment with legal and operational standards.
Apr 3, 2025, 11:04 AM UTC
This document serves as Amendment II to a federal solicitation, specifically addressing vendor inquiries and providing the Government's responses. Key clarifications include that the National Institute of Standards and Technology (NIST) will review each deliverable within three weeks, which should be factored into the schedule. Critical components such as the System on Module (SOM) and memory chip mounting socket will be supplied by NIST, alleviating the vendor's need to include them in their pricing. Furthermore, the exact model of the Zynq SOM is specified, and there are no size constraints for the main printed circuit board (PCB). Vendors are required to download necessary firmware from the SOM vendor's website, while collaborative testing and integration are anticipated, with NIST overseeing specific testing while expecting the PCB designer to manage power sequencing and signal integrity. All other terms and conditions in the solicitation remain unchanged, indicating continuity and clarity for potential vendors involved in this contract. This amendment highlights the importance of effective communication and collaboration in achieving project objectives within the federal contracting process.
Apr 3, 2025, 11:04 AM UTC
This government document titled "AMENDMENT 0003" addresses key technical specifications and clarifications related to a Request for Proposal (RFP) concerning the integration of an Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) module with memory devices. It outlines that the System on Module (SOM) pricing should not be included in board unit costs as such components are provided under the contract. The document further defines that instructions for the ADC-DAC will be transmitted via a 40MHz SPI interface from the FPGA board. It confirms that the external system is a host PC, which will receive characterization outputs through an Ethernet or USB interface. Additionally, it specifies that the memory modules are integrated within the ADC-DAC board and that FPGA will communicate data to and from the memory module through DACs and ADCs, respectively. The maximum operational frequency of supported memory devices such as RRAM and MRAM is established to be 200MHz, with the National Institute of Standards and Technology (NIST) responsible for providing ADC and DAC part numbers and sockets. This document serves to ensure clarity for potential vendors in meeting the project's technical requirements while facilitating compliance with government procurement protocols.
Apr 3, 2025, 11:04 AM UTC
This document is an amendment related to a procurement request by the National Institute of Standards and Technology (NIST). It addresses technical inquiries regarding the use of certain hardware components for a prototyping project. NIST will supply the System on Module (SOM) and specifies the selection process that points users to the Ultrazed platform. It requires Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) with parallel programming capabilities, while noting their current use of devices that require serial programming. Additionally, the document outlines that signal integrity simulation is necessary for the motherboard PCB design, while functional verification testing is deemed sufficient for the custom-designed product. Early collaboration through an acceptance test plan with technical contacts is endorsed to ensure adherence to specifications throughout the project lifecycle. The content reflects typical elements of government RFPs and grants, focusing on clear technical specifications and collaborative project management to meet federal standards.
Apr 3, 2025, 11:04 AM UTC
The National Institute of Standards and Technology (NIST) requires the design, fabrication, and assembly of a memory characterization board as part of its metrology program. The board, based on Field Programmable Gate Array (FPGA) technology, will facilitate the evaluation of custom analog memory devices developed by researchers and industry. The project includes the development of schematics and layouts, signal integrity analysis, board fabrication, and testing, with deliverables required within specified timelines. The contractor must ensure high standards in physical design and signal integrity and deliver ten fabricated boards, all documented and packaged per NIST guidelines. Performance testing, damage inspection, and acceptance criteria are outlined, along with warranties and payment terms. Additionally, cybersecurity measures are mandated to protect sensitive data in line with federal standards. This project represents a significant step in advancing memory device characterization, aiding both research and industrial applications.
Lifecycle
Title
Type
Combined Synopsis/Solicitation
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