Release Date
November 29th, 2023
Open Date
January 3rd, 2024
Due Date(s)
February 21st, 2024
Close Date
February 21st, 2024
Topic No.


Monolithic SDR SoC for SATCOM


Department of DefenseN/A


Type: STTRPhase: Phase IYear: 2024


The Department of Defense (DOD) is seeking proposals for the development of a monolithic Radio Frequency (RF) System-on-Chip (SoC) Software Defined Radio (SDR) Integrated Circuit (IC) transceiver for satellite communications (SATCOM). The technology should meet specific defense needs and support global navigation satellite system (GNSS), internet-of-things (IoT) edge-computing, and artificial intelligence (AI) processing technologies and applications. The objective is to optimize the size, weight, and power (SWaP) of the device for low SWaP DoD applications. The Phase I effort will focus on feasibility, technological issues, and developing a Phase II proposal. The Phase II effort will involve executing the proposed developmental activities, demonstrating working silicon, and developing a Phase III commercialization plan. The Phase III effort will pursue commercialization objectives and may include non-SBIR/STTR funded R&D or production contracts. The project duration is not specified, and funding specifics can be found on the solicitation agency's website.



Electronics | Space Platforms



Microelectronics | Space Technology



Development of a monolithic Radio Frequency (RF) System-on-Chip (SoC) Software Defined Radio (SDR) Integrated Circuit (IC) transceiver for satellite communications (SATCOM) meeting specific defense needs and supportive of global navigation satellite system (GNSS), internet-of-things (IoT) edge-computing, and artificial intelligence (AI) processing technologies and applications.



The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with section 3.5 of the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.



There are few commercially available, monolithic, SDR-SoCs on the market [1][2], and those that exist, though highly capable, can be cost prohibitive and are not optimized for low size, weight, and power (SWaP) DoD applications, such as small handheld devices where ultra-low power and reduced form-factor are major design considerations. Furthermore, a review of prior awarded SBIR/STTR topics demonstrates that defense specific needs for low SWaP SDR devices have routinely been met through a modular approach of integrating commercial-of-the-shelf (COTS) devices [3]. However, further SWaP optimization can only be achieved through higher levels of SoC integration with efficient architecture execution in supportive modern semiconductor technologies that include sufficient intellectual property (IP) offerings. Though SDR construction varies, the typical SDR architecture consists of a RF frontend, a field programmable gate array (FPGA) for baseband signal processing, and microprocessor or microcontroller for SDR control and power management. While continued advances in analog-to-digital (ADC) converter and digital-to-analog converter (DAC) designs have fueled RF SoC frontend innovations, such as direct-sampling of RF signals [4][5], and with the availability of processor core IP more commonplace in modern technology nodes, FPGA fabrics may not be most effective for on-chip baseband signal processing. While FPGAs are capable of meeting the high performance and reconfigurability requirements of SDRs, this comes at the expense of area and power dissipation due to their inherent structure. Furthermore, the powerup and reconfiguration latencies of FPGAs can be an issue in applications where wakeup time and agile tuning are required. To address these issues, taking advantage of advances in semiconductor scaling, application specific baseband processing, typically accomplished by the FPGA, may be more efficiently accomplished through on chip digital signal processing (DSP) techniques.



The purpose of the Phase I effort is to: determine the feasibility (cost, schedule, and performance) related to the development of the SDR-SoC; identify technological issues (availability of IP, etc.) to be addressed through innovations; and, develop a Phase II proposal for development activities toward the realization of the SDR-SoC from design to qualification, with the goal of meeting the following performance specifications:



a. Off-state leakage current: < 10 µA

b. Sleep conditions must be specified along with projected sleep current.

c. Active power management with ability to shutdown/sleep system components.

d. Peak Power Dissipation: < 1 W

e. Chip area: 5mm x 5mm


RF Frontend:

a. Transceiver tuning range: 100 MHz to 6 GHz

b. At least 1 Tx and 1 Rx channel

c. 40MHz Bandwidth

d. Anti-aliasing filters

e. 14 bit DAC, 14 bit ADC or better


DSP Engine

a. Programmable DSP module floating point, 64 MACs running at 500MHz or better.


Processor Core:

a. ARM Cortex9 or better or RISC-V core with support for bootable Linux OS, external storage, UART, USB, I2C, SPI, network interfaces.

Furthermore, due to national security considerations use of the Trusted Foundry Program, foundry access (GLOBALFOUNDRIES) is preferred, but not required, when considering feasibility options. Phase-I feasibility study should also be inclusive of programming software for the DSP module and front end, and supported Linux distribution(s).



The purpose of the Phase II effort is to: execute on the Phase I proposed developmental activities and innovations needed to advance the SDR-SoC concept; demonstrate working silicon; and develop a Phase III product commercialization plan, including potential non-DoD customers. Phase II outcomes will result in the design for fabrication, fabrication, package, assembly, test, qualification, and delivery of functional prototypes, including supporting design development and user-required software, data, and documentation, of either the fully functional monolithic SDR-SoC or necessary IP block(s) required to advance the monolithic SDR-SoC concept.



The objective of Phase III effort is to pursue commercialization objectives resulting from the Phase II developments. Other Phase III activities may include follow-on non-SBIR/STTR funded R&D (ATSP, OTA) or production contracts for developed products intended for use by the DoD.



  1. Xilinx, August, 2023.

  2. Analog Devices, August, 2023.

  3. DoD SBIR/STTR Program, SBIR/STTR Award Data search,

  4. search keywords: SDR, SDR + Low SWaP, SDR + SATCOM: August, 2023.

  5. A. M. A. Ali et al., "A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration," in IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3210-3224, Dec. 2020, doi: 10.1109/JSSC.2020.3023882.

  6. L. Fang, X. Wen, T. Fu and P. Gui, "A 12-Bit 1 GS/s RF Sampling Pipeline-SAR ADC With Harmonic Injecting Cross-Coupled Pair Achieving 7.5 fj/Conv-Step," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 8, pp. 3225-3236, Aug. 2022, doi: 10.1109/TCSI.2022.3169508.



Software Defined Radio (SDR); System on Chip (SoC); Satellite Communications (SATCOM); Integrated Circuit (IC); Internet of Things (IoT); edge computing; Artificial Intelligence (AI); Global navigation satellite system (GNSS).