RISC-V High Assurance FPGA Softcore Aberdeen Architecture
ID: A244-045Type: BOTH


RISC-V High Assurance FPGA Softcore Aberdeen Architecture


Department of DefenseN/A


Type: SBIRPhase: BOTHYear: 2024
  1. 1
    Release Oct 3, 2023 12:00 AM
  2. 2
    Open Oct 3, 2023 12:00 AM
  3. 3
    Next Submission Due Mar 31, 2025 12:00 AM
  4. 4
    Close Mar 31, 2025 12:00 AM

The Department of Defense (DOD) is seeking proposals for the topic "RISC-V High Assurance FPGA Softcore Aberdeen Architecture" as part of its SBIR program. The objective of this research topic is to develop a softcore processor based on the concepts presented in existing patents and the RISC-V instruction set architecture. The government will provide a non-exclusive, royalty-free license for the necessary patents to the phase I contractor(s) for 10 years. The research team will investigate the feasibility of developing the Aberdeen Architecture, including its high assurance capabilities, state machine monitoring parallelism, and potential for low latency security policies. In phase II, the team will develop an FPGA softcore implementation and software compiler, delivering prototype systems and providing training. The ultimate goal is to commercialize the Aberdeen Architecture for both government and commercial applications in fields such as banking, communications, medical electronics, and aerospace. The solicitation is open until March 31, 2025. For more information, visit the SBIR topic link here or the DOD SBIR/STTR opportunities page here.

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