The Department of Defense, through the Defense Microelectronics Activity (DMEA), is seeking innovative solutions for the modeling, optimization, and monitoring of thick Silicon Carbide (SiC) epitaxy processes under the Small Business Innovation Research (SBIR) program. The objective is to develop a software solution that enables in-situ process characterization and real-time adjustments during the Chemical Vapor Deposition (CVD) of thick SiC epilayers, enhancing efficiency, reducing waste, and improving the quality of the deposited materials. This technology is crucial for advancing DoD capabilities and commercial applications, particularly in the development of ultra-high power SiC devices. Interested parties should note that the solicitation is currently closed, with the application due date having been September 10, 2024. For further details, please refer to the official solicitation page at https://www.dodsbirsttr.mil/topics-app/.

## Description

The technology shall provide in-situ process characterization and monitoring of key parameters over the entire duration of the epilayer deposition, which is expected to take several hours per wafer depending on the gas chemistries used. Maximum achievable growth rates are desired while also preserving stable process conditions to avoid unwanted changes to the surface morphology of the epilayer, nucleation of defects, and poor electrical characteristics such as decreased net carrier concentration [1, 2]. Unlike standard process monitoring tools that are limited to feed-forward and feedback, this technology will perform real-time process adjustments account for changing process conditions within the chamber such as fluctuations in temperature, pressure, rotation, or flow rates due to degradation of chamber hardware.The technology will utilize captured Design of Experiment (DOE) data to determine which process parameters strongly correlate to defect densities and other undesirable film characteristics. The software will find the ideal settings for each control setting to optimize the chamber conditions. Once a particular epi process has been established, the DOE data can then be applied to a wafer-to-wafer Artificial Intelligence (AI) process control algorithm for continued monitoring, precluding the need for test runs or chamber seasoning prior to running various process types/epilayer stacks categorized by dopant, concentration, and layer thickness. A model of the epi process will be output to a workstation accessible to process engineers. This feature serves to improve process engineers&rsquo; understanding of the growth process and guides efforts to optimize conditions resulting in less wasted material when changes need to be implemented.The technology should enable unmonitored wafer processing for additional throughput (no human in the loop). The software will have prognostic capability to perform in-situ process modification and may require the implementation of an AI/ML algorithm. Sensor data will be transferred from epi equipment via Semiconductor Equipment Communications Standard-Generic Equipment Model (SECS-GEM) protocol. Other sensor inputs will be integrated as needed. Example process conditions fed through sensor readings include chamber temperature, pressure, gas flows, etc.All process conditions and trace data should be captured for Advanced Process Control (APC), including Run-to-Run (R2R), Fault Detection and Classification (FDC), and Statistical Process Control (SPC). Process conditions should be compared against resultant defect density in the deposited epilayer. 

## Objective

The DoD is seeking the development of a process control and modeling solution to aide in the start-up and monitoring of a hot-walled Chemical Vapor Deposition (CVD) Silicon Carbide (SiC) epitaxy process, whereby very thick SiC epilayers will be grown on 150mm base wafers. A successful solution will serve to accelerate start-up of new processes, optimize quality of deposited epilayers, maximize wafer throughput where possible, minimize material waste and downtime, and continuously monitor wafer production. 

## Phase I

Conduct a feasibility study and design a software solution.The solution&rsquo;s architecture, design and operation should be defended against the following metrics: 1.&emsp;Reduction of waste: fewer runs required to optimize process conditions resulting in fewer scrapped or wasted substrates and other consumables. 2.&emsp;Cost savings: lower consumable usage, fewer wafers required for start-up and epilayer development. 3.&emsp;Time savings: accelerate equipment start-up and development. 4.&emsp;Accuracy of the models to deposited epilayers. 5.&emsp;Reduction of defect densities in the epilayer through process optimization. 6.&emsp;Expected efficiencies in production.The solution should also describe how the software will be implemented into a production wafer foundry environment, including integration into Manufacturing Executive Systems (MES). Time required to train models should be indicated. A supportability model of the developed solution should also be outlined. Expected level of training and skills required for operation should be described. If existing solutions are being leveraged to develop the solution, a description of those tools should be included. Describe the materials, DOEs, etc., required for training the models, including what inspection and metrology data is required: thickness defect mapping and classification, bow, warp, Total Thickness Variation (TTV), etc.The delivered report should define a program plan for follow-on phase development. If any of the above items cannot be fully addressed, the report must include relevant research and rationale that demonstrates their inapplicability to the proposed technique. If adhering to the above items is possible, but not financially feasible, the report must include relevant justification. Finally, the challenges and special considerations for implementing the solution into an existing fabrication facility should be addressed. 

## Phase II

Build, test, and implement a functional solution that meets the requirements listed in Phase I. Demonstrate the capability of performance on a commercial single-wafer, hot-walled epi reactor of DMEA&rsquo;s choosing.The final report should address all steps required and issues encountered during implementation, including recommended hardware for optimal performance at a user facility.

## Phase III: Dual Use Applications

This technology could be utilized for DoD and commercial applications requiring the growth of thick SiC epilayers. SiC is a key enabling technology for next-generation DoD systems. Ultra-high power SiC devices will eventually find their way into grid applications and other commercial use cases driven by power efficiency and portability. A detailed commercialization plan should be designed and executed in this phase, including researching potential DoD and commercial applications, marketing to the respective customers, development of relevant prototypes, demonstration of performance, documentation of relevant details, and benefits to end users.Deliver a detailed report that documents the market research methods used, the findings of the market research, potential use cases, and details of prototypes with descriptions, marketing, and other commercialization activities.

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