The Department of Defense (DoD), specifically the United States Air Force (USAF), is seeking proposals for the development of advanced Digital-to-mm-Wave Digital-to-Analog Converters (DACs) and Analog-to-Digital Converters (ADCs) as part of its Small Business Innovation Research (SBIR) program. The objective is to create fully integrated converter architectures that enhance the performance of direct-RF beamforming transceivers, which are critical for airborne and spaceborne sensing, electronic warfare, and communications. This initiative aims to address the limitations of current data converters by developing high-performance solutions that meet stringent specifications, including high bandwidth and low power consumption, while also creating cross-domain functional models for system-level simulations. Proposals are due by June 25, 2025, with the opportunity set to open on May 28, 2025. For more information, interested parties can visit the SBIR website at https://www.dodsbirsttr.mil/topics-app/.

## Description

Element-level digital beamforming has shown significant reduction in size, weight, and mechanical complexity when compared with traditional analog or digital sub-array architectures. In these element-level radar and EW systems, analog manifolds, RF receiver-exciters, and analog phase shifting are replaced with high-bandwidth data converters followed by high-throughput digital processing [1]. This shift has improved the agility and adaptability of phased array systems [2]; however, data converter performance is a limiting factors in element-level beamforming. Data converters with high instantaneous bandwidth (&gt;4 GHz), millimeter wave (mmWave) signal acquisition (up to 45 GHz), low transceiver power (&lt;400 mW per transceiver channel), high resolution (&gt;6.5 Effective Number of Bits), and high linearity (&gt;65 dB Spurious Free Dynamic Range) are needed for future airborne, spaceborne, low power, and attritable applications. To meet these performance challenges in a mixed-signal transceiver block, both the Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) will require novel methods of up-conversion, calibration, element-level synchronization, low power data processing, and other improvements to current data converter architectures. In addition to the design of a direct Digital-to-mm-Wave ADC and DAC, the development of high-fidelity cross-domain models for the data converters is also required. Such models will provide visibility into the digital hardware, analog/RF hardware, and the software needed to integrate advanced mmWave data converters and will support architectural trade-offs and performance simulations at the system level (e.g. element synchronization, multi-element beamforming, agile spectrum allocation, etc.), enabling the rapid and virtual integration and prototyping of mmWave transceivers.

## Objective

This topic seeks the development of advanced architectures for fully integrated Digital-to-mm-Wave Digital-to-Analog Converters (DACs) and Analog-to-Digital Converters (ADCs) for use in direct-RF beamforming transceivers (TRX). These advancements would have significant impact in the performance of DoD airborne and spaceborne sensing, electronic warfare capability, and communications effectiveness. This DAC and ADC development will be accompanied by the creation of corresponding cross-domain functional models which enable a high-fidelity system-level simulation of multiple TRXs channels, supporting rapid analysis of benefit, system integration planning, and insertion into identified DoD systems. 

## Phase I

In this initial phase, the DAC and ADC architectures will be explored, the fabrication technology selected, and simulations using current mix-signal design best-practices will be conducted. These simulations will demonstrate the ability of the converter architectures to meet the design specifications laid out in the description. From this exploration, design trade-offs and technical risks will be documented, circuit architectures and design strategies will be established, and cost/schedule estimates for Phase II will be outlined. Additionally, the digital-engineering strategy for the DAC and ADC cross-domain functional models will be established to support future virtual integration and prototyping efforts. in Phase II.

## Phase II

Under Phase II, the full design of the DAC and ADC will be completed; layouts will be finalized and submitted for fabrication. During the fabrication process, the cross-domain functional models will be developed, demonstrating both close comparison to the mixed-signal simulations and scalability for full-system modeling and architecture evaluation. Upon receipt of the manufactured prototype, initial testing will be used to confirm part yield, general functionality, and initial specification compliance. 

## Phase III: Dual Use Applications

The awardee(s) will fully test the prototype fabricated in Phase II, demonstrating the capability of the DAC and ADC against the desired specifications and feasibility for potential transition. The test results will be compared to the prefabrication simulations and reported with discrepancies addressed. Additionally, the results will be used to baseline the cross-domain functional model to be used in future system development efforts. The DAC and ADC will be refined with feedback from testing, and the design will be prepared for higher rate fabrication. Commercialization of this technology for transition to government and civilian use is encouraged at this phase and access to potential users and applications will be provided. Opportunities for Phase III awards for additional research, capability development, services, or direct procurement of IP will be possible.

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