The Department of Defense, specifically the United States Air Force, is seeking proposals for the development of a Room Temperature Quantum Cascade Laser Array under the Small Business Innovation Research (SBIR) program. The objective is to create a high-efficiency array of quantum cascade lasers that operate at room temperature, addressing the limitations of current infrared scene projection technologies used in military testing. This initiative is crucial for enhancing optical sensor systems, as it aims to overcome issues such as low wall plug efficiency and high costs associated with existing infrared light emitting devices. Interested parties should note that the solicitation number is AF25D-T010, with a release date of May 7, 2025, and applications due by June 25, 2025. For more information, please visit the official source link at https://www.dodsbirsttr.mil/topics-app/.

## Description

Military testing of optical sensor systems relies heavily on infrared scene projection in a hardware in the loop test environment [1]. Traditionally, infrared scenes were generated using an array of micro resistors (resistor array) which is insufficient for high brightness targets and high frame rates, and suffers from excessive heat generation [2]. Much research and development has been applied to infrared light emitting devices (IR LEDs) to meet the technology gap and development is still active [3]. IR LEDs suffer from poor wall plug efficiency and high cost.As an enhancement to existing infrared scene projection technologies and as a technology enabler, it is desired to develop a quantum cascade micro laser array that overcomes most or all of the disadvantages of the most prominent projector technologies. Unfortunately, micro laser arrays also introduce their own issues, including the presence of speckle in projection output and low yield in large array devices. To improve manufacturability of arrays, with significant resulting utility, a scaled down array with larger pitch is desired, using a tiling capability to increase array format when larger arrays are needed.For this effort, some tradeoff is allowed between the following requirements. A small format (small pitch) laser array is desired for illumination purposes in the 3.8&mu;m to 4.2&mu;m spectral band or at 4.6&mu;m. Broadened laser lines are acceptable as long as they are single mode output and stable over the output power range. The laser array is desired to be square with minimum pixel format of 10x10 and maximum format 100x100, comprised of individually addressable laser devices of pitch between 50&mu;m and 120&mu;m, output power around 70&mu;W (each) in single mode, continuous wave (CW) operation, and can support modulation of up to 1MHz (and provides the ability to synch individual lasers to a system frequency). Further requirements are to develop a room temperature design that has very high wallplug efficiency (&amp;gt;20% wall plug efficiency has been demonstrated in single devices, out of band [4], ~3% in the desired band [5] and may be reduced in the array format), is tunable (to other output wavelengths), is low cost and high yield fabrication that is scalable, with a form factor that supports &ldquo;tiling&rdquo; of laser arrays into a larger format array. It is desirable for each individual laser to have output power characteristics that are highly linear and exhibit high power stability over the entire output range. Spectral output may be single line within the band given or may be broadened within that band, though the spectral distribution must remain approximately constant in all operational conditions (no line shifting or broadening as power is increased). Low spatial coherence properties are desired (but not required) from each individual laser. Program emphasis will be on system level (laser array + controller) performance, moderate to high volume production and reduction of cost. Laser technologies other than quantum cascade laser will be considered if wall plug efficiency is very high. LEDs are not acceptable for this program.

## Objective

Develop a concept and demonstrate a high efficiency array of quantum cascade lasers operating at room temperature.

## Phase I

At a minimum for Phase 1, initial designs will be developed and thoroughly evaluated through modeling and simulations, though preference will be given to actual hardware feasibility demonstration. Concept performance will be evaluated based primarily on pixel pitch and format, output modes and power, spectral characteristics and stability of output. Consideration is also provided for manufacturability, design/manufacturing/operation complexity, ability to scale to larger devices and tunability to reach other bands as desired. 

## Phase II

Refinement of a concept, design, fabrication/demonstration of a prototype and prototype testing will constitute the majority of the Phase 2 effort. All testing is expected to be performed at the firm&rsquo;s site, with the firm&rsquo;s equipment (no Government supplied equipment). Any remaining concept refinements needed after a Phase 1 completion will be addressed early in the Phase 2 effort, ideally in parallel with the design efforts. The design process should include planning for demonstration and testing/measurements. Fabrication and demonstration of a prototype is expected to require a substantial portion of the phase 2 program due to component purchase lead times and several iterations of fabrication to refine the process. With proper planning for demonstration and testing, the final portion of the phase 2 program should be relatively short and produce high quality data that indicates the designed items function as intended. 

## Phase III: Dual Use Applications

Outputs from Phase 2 are anticipated to be TRL 7 but may require additional effort to refine to a more manufacturable design. Phase 3 will concentrate on the manufacturability as well as the fabrication process itself to prepare the vendor to commercially offer a fully functional product. A final product is expected to be demonstrated and marketed to AFRL and transition partner in the 782d Test Squadron. Additional Phase 3 planning will occur during the Phase 2 process once a design is established and manufacturing requirements and manufacturability become more apparent.

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