The Department of Defense, through the Defense Advanced Research Projects Agency (DARPA), is seeking proposals for the Small Business Innovation Research (SBIR) program focused on the development of on-chip wavelength generation for Dense Wavelength Division Multiplexing (DWDM) photonic transceivers. The objective is to create integrated photonic transceivers that incorporate multi-wavelength comb generation, which are essential for advanced data processing, sensors, and high-performance optical interconnect solutions. This initiative aims to overcome existing barriers in the commercial availability of efficient WDM sources, thereby enhancing the scalability and reliability of optical interconnects in both military and commercial applications. Proposals are due by June 25, 2025, with the program's release date set for May 7, 2025, and interested parties can find more information at the DARPA SBIR website.

## Description

The DARPA Photonics in the Package for Extreme Scalability (PIPES) program seeks to enable next-generation microelectronics with co-packaged optical I/O for future high-performance DoD and commercial systems. Short reach optical interconnects have historically utilized a small portion of the optical spectrum, with current architectures using only one to a few wavelengths per fiber. Under the PIPES program, DARPA has developed systems utilizing 16-, 32-, and 64-wavelength WDM. However, external multi-wavelength laser sources are highly customized, require complex stabilization control and suffer from low reliability and high cost. Moreover, the laser-to-transceiver optical coupling adds significant losses to the system link budget. The lack of commercial availability of efficient and robust WDM sources presents a significant barrier for adoption of co-packaged optical interconnect solutions. This SBIR program seeks on-chip co-integration of multi-wavelength comb generation with the photonic transceiver. The preferred optical solution is monolithic photonic integrated circuit (PIC). Both externally pumped wavelength comb generators residing on-chip and on-chip integrated laser arrays will be considered. If die-to-die bonding is proposed, the optical coupling losses cannot exceed 0.5 dB. A separate die for the electronic functions is anticipated in the form of an electronic integrated circuit (EIC) and it must be packaged with the PIC using commercially available microelectronics packaging. Specifically excluded are any approaches utilizing comb-to-PIC fiber coupling or photonic wire-bonding, as well as any optical amplification that is not directly integrated on the same PIC. The only external component, coupled by fiber is expected to be a pump laser (if applicable). The development of a pump laser is excluded on this SBIR and shall be sourced as an individually packaged, commercially available off-the-shelf component. Proprietary pump laser solutions that cannot be procured on the open market will not be considered. The technical approaches to on-chip multi-wavelength sources shall be compatible with chip-scale fabrication and integration methods. Solutions developed under this topic shall deliver multiple laser channels (= 16 wavelengths) on a regular frequency grid (nominally 100-400 GHz spacing) in the O-band and/or C-band of the spectrum. The multi-wavelength sources are expected to provide power levels per wavelength channel sufficient to meet the end-to-end optical link budget with margin, as specified in Table 1 below. 

## Objective

Develop and demonstrate prototype integrated photonic Dense Wavelength Division Multiplexing (DWDM) transceivers with on-chip wavelength generation. Such integrated photonic transceivers are critical for co-packaged optical interconnect solutions, advanced data processing, sensors, and other emerging multi-wavelength photonics applications.

## Phase I

Proposers must show a feasible path for DWDM photonic transceivers with on-chip wavelength generation architecture that addresses Phase II program metrics listed in Table 1. Scalability of the architecture for achieving 4T aggregate bandwidth per photonic die in a follow-on effort should be discussed as a part of the Phase I report. Documentation in support of the architecture feasibility should include all relevant information including, but not limited to technical reports, characterization data from hardware demonstrations of multi-wavelength lasers with similar characteristics, and detailed modeling/fabrication results that delineate a direct path from prior experimental results to the program metrics. Phase I fixed payable milestones shall include: Phase I Schedule/Milestones/Deliverables <ul><li>Month 1: Report on initial architectures and approaches to Photonics Integrated Circuit (PIC), Electronic Integrated Circuit (EIC). </li><li>Month 3: Interim report describing the prototype system details with fabrication, integration and assembly strategies developed. </li><li>Month 6: Final Phase I Report summarizing approach; prototype architectures and integration strategy; quantification of expected performance based on detailed system modeling; results from initial test structures characterization; comparison with alternative state-of-the-art methodologies.</li></ul>

## Phase II

The focus of the Phase II effort is to exploit concepts and technologies for co-integration of multi-wavelength comb generation with the transmitter/receiver PIC and transform them into robust, manufacturable DWDM modules. The transceiver modules delivered at the end of Phase II must be self-contained, environmentally robust, and meet the following minimum performance metrics:&nbsp;Table 1. On-chip wavelength generation for DWDM photonic transceivers SBIR, Phase II Metrics<figure class="table" style="float:left;"><table style=";"><tbody><tr><td style="border:1.0pt solid windowtext;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">Metric</td><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:none;border-right-style:solid;border-top-style:solid;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">Target*</td></tr><tr><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:solid;border-right-style:solid;border-top-style:none;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">operating wavelength</td><td style="border-bottom:1.0pt solid windowtext;border-left-style:none;border-right:1.0pt solid windowtext;border-top-style:none;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">O-band and/or C-band</td></tr><tr><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:solid;border-right-style:solid;border-top-style:none;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">number of wavelength channels</td><td style="border-bottom:1.0pt solid windowtext;border-left-style:none;border-right:1.0pt solid windowtext;border-top-style:none;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">≥ 16†</td></tr><tr><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:solid;border-right-style:solid;border-top-style:none;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">wavelength channel spacing</td><td style="border-bottom:1.0pt solid windowtext;border-left-style:none;border-right:1.0pt solid windowtext;border-top-style:none;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">regular grid, multiple of 100 GHz spacing</td></tr><tr><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:solid;border-right-style:solid;border-top-style:none;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">data rate per wavelength</td><td style="border-bottom:1.0pt solid windowtext;border-left-style:none;border-right:1.0pt solid windowtext;border-top-style:none;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">≥ 32 Gbps†</td></tr><tr><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:solid;border-right-style:solid;border-top-style:none;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">link bit-error rate (BER)</td><td style="border-bottom:1.0pt solid windowtext;border-left-style:none;border-right:1.0pt solid windowtext;border-top-style:none;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">10-12</td></tr><tr><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:solid;border-right-style:solid;border-top-style:none;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">aggregate bandwidth per fiber</td><td style="border-bottom:1.0pt solid windowtext;border-left-style:none;border-right:1.0pt solid windowtext;border-top-style:none;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">≥ 512 Gbps†</td></tr><tr><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:solid;border-right-style:solid;border-top-style:none;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">number of fibers per module</td><td style="border-bottom:1.0pt solid windowtext;border-left-style:none;border-right:1.0pt solid windowtext;border-top-style:none;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">1 TX, 1 RX, 1 pump laser (if applicable)</td></tr><tr><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:solid;border-right-style:solid;border-top-style:none;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">link budget, point-to-point</td><td style="border-bottom:1.0pt solid windowtext;border-left-style:none;border-right:1.0pt solid windowtext;border-top-style:none;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">2 fiber couplers, 100 meters of standard single mode fiber, 2 dB link margin</td></tr><tr><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:solid;border-right-style:solid;border-top-style:none;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">link efficiency</td><td style="border-bottom:1.0pt solid windowtext;border-left-style:none;border-right:1.0pt solid windowtext;border-top-style:none;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">3 pJ/bit</td></tr><tr><td style="border-bottom-style:solid;border-color:windowtext;border-left-style:solid;border-right-style:solid;border-top-style:none;border-width:1.0pt;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:189.35pt;">data interface</td><td style="border-bottom:1.0pt solid windowtext;border-left-style:none;border-right:1.0pt solid windowtext;border-top-style:none;height:13.45pt;padding:0in 5.4pt;vertical-align:top;width:237.9pt;">UCIe compliant§</td></tr></tbody></table></figure>&nbsp;* Performance metrics are measured for an end-to-end link operating at all wavelength channels† Proposals exceeding the minimum 16 channels and/or 32 Gbps/channel are encouraged§ Fully implemented data interface is not required. However, design and simulation of the proposed interface is required.&nbsp;Target characteristics of the proposed transceiver components (EIC, PIC, fiber connectors, pump laser, thermal management, etc.) shall be specified by the Proposer. Proposals shall highlight the technical path to reach the performance metrics described above.&nbsp;Schedule/Milestones/DeliverablesIn the Phase II Base effort (18 months), the expected emphasis is on component design, fabrication, and characterization. The Phase II Option effort (6 months), if awarded, shall be focused on packaging and characterization of the deliverables. Given the aggressive schedule, Proposers must outline a clear path to deliver hardware prototypes within 24 months. By program end, Performers must deliver ten (10) transceiver prototype units with electronic control and optical fiber outputs. In addition to monthly reporting and quarterly reviews with DARPA, Phase II fixed milestones for this program shall include:&nbsp;Phase II Base<ul><li>Kickoff: System Requirements Review (SRR), to include risk analysis.</li><li>Month 3: Report detailing the design specifics of multi-wavelength transceiver system, including PIC and EIC device layout, detailed fabrication flow, and test plan.</li><li>Month 6: Documented completion of finalized device design and component layouts; PIC and EIC tapeout report.</li><li>Month 9: Market Study Report on application requirements, potential customers, and commercialization strategy.</li><li>Month 12: Electronics Report describing control electronics requirements, post-tapeout simulation results, and assembly plan.</li><li>Month 15: Photonics Report detailing requirements, post-tapeout simulation results, and package design.</li><li>Month 18: Demonstration of multi-wavelength transceiver module meeting program metrics; Final Report for Phase II Base Period to include characterization data for the integrated multi-wavelength transceiver. Preliminary design of UCIe compliant data interface.</li></ul>Phase II Option <ul><li>Kickoff: Design Review of packaged prototypes.</li><li>Month 21: Prototype Design Report documenting the design specifics of hardware deliverables (Photonics + Electronics + Packaging).</li><li>Month 24: Delivery of 10 packaged devices to DARPA or US Government Partner*; Final Program Report including fabrication process details and characterization data for delivered prototypes.</li></ul>* All prototypes shall be provided with adequate instructions to support government testing and evaluation using standard laboratory equipment. The components included are expected to meet the program metrics.

## Phase III: Dual Use Applications

Phase III work is typically oriented towards commercialization of SBIR/STTR research or technology with funding obtained from either the private sector, a non-SBIR/STTR Government source, or both, to develop the technology into a viable product for sale in military or private sector markets. It is envisioned that the technology developed under the SBIR program will have dual-use commercial and DoD applications. In the commercial space, the transceiver platform will be a foundational building block for data center and high-performance computing optical interconnect. Multi-wavelength interconnects are expected to be critical enablers for optical transport in datacom, computing, and electronic processing systems. In the DoD, the multi-wavelength transceivers are anticipated to be a key building block for high-throughput interconnect in high-performance computing, edge processing, emerging artificial intelligence (AI) and machine learning (ML) systems, and sensors.

ON-CHIP WAVELENGTH GENERATION FOR DWDM PHOTONIC TRANSCEIVERS

SBIR Opportunity Analysis

SBIR Documents

Related SBIR/STTR Opportunities

Opportunity Snapshot

Key Dates