The Department of Commerce, specifically the National Institute of Standards and Technology (NIST), intends to noncompetitively acquire specialized silicon wafers with multiple thin films for its Biomedical Measurement Technologies Group. The procurement aims to obtain test substrates essential for assessing the stability and reliability of biomolecule attachment to semiconductor surfaces, which is crucial for developing effective biosensors within the CHIPS program. These substrates must be manufactured on high-quality semiconductor fabrication lines and meet specific technical specifications, including various patterned and blanket films of Hafnium Oxide, Silicon Dioxide, and Gold on 200 mm silicon wafers. Interested parties capable of meeting these requirements are encouraged to respond by submitting their information to Nina Lin at nina.lin@nist.gov, as the government will consider responses to determine if a competitive procurement is feasible.

Notice of Intent to Noncompetitively acquire Semiconductor Wafers with Multiple Thin Films.

This notice is not a request for a quotation. A solicitation document will not be issued, and quotations will not be requested.

This acquisition is being conducted under the authority of FAR 13.106-1(b). The North American Industry Classification System (NAICS) code for this acquisition is 334413, Semiconductor and Related Device Manufacturing which has a small business size standard of 1,250 employees.

The semiconductor supply chain is global, specialized, and interconnected. Chipmakers do business with thousands of individual suppliers that provide the highly complex materials and tools used to produce semiconductors. To address the lack of full visibility into the semiconductors markets supply chain and R&D ecosystem gaps the National Institute of Standards and Technology (NIST) will conduct the measurement science, or metrology, critical to the development of new materials, packaging, and production methods in chip manufacturing. 

With this goal, the NIST Biomedical Measurement Technologies Group within the Microsystems and Nanotechnology Division of the Physical Measurement Laboratory (PML) requires specialized test substrates composed of silicon wafers enhanced with multiple thin films. These substrates are a critical component of a CHIPS program to assess the functionalization of semiconductor substrates with passivation and biorecognition elements to advance measurements of manufacturable CMOS biosensors.

This project aims to rigorously assess the stability and reliability of biomolecule attachment to semiconductor surfaces, which is vital for the development of effective biosensors. The substrates required will serve as an industry reference point for NIST's internal samples. As such, they must be manufactured on high-quality foundry or research-grade semiconductor fabrication lines capable of processing 200 mm silicon wafers. The thin films must be applied either uniformly as a continuous layer over the entire wafer surface or in a precise patterned layout using either optical or e-beam lithography, depending on the specific requirements outlined in the specifications below.

The Contractor shall provide test substrates that meets all technical specifications and performance specifications identified below:
 

A) Patterned films comprising 3 nm Hafnium Oxide (HfO2) on 2 nm Silicon Dioxide (SiO2) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).
SiO2 thickness: 2 nm nominal with structures patterned using optical lithography.
HfO2 thickness: 3 nm nominal with structures patterned using optical lithography.
Patterns: Patterns in the micrometer size either as lines, squares or rectangles defined using optical lithography.


B) Blanket films comprising 3 nm Hafnium Oxide (HfO2) on 2 nm Silicon Dioxide (SiO2) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).
SiO2 thickness: 2 nm nominal blanket with no patterning.
HfO2 thickness: 3 nm nominal blanket with no patterning.


C)  Blanket films comprising 2 nm Silicon Dioxide (SiO2) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).
SiO2 thickness: 2 nm nominal blanket with no patterning.


D)  Blanket films comprising Gold (Au) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).

E) Blanket films comprising amine terminated self-assembled monolayers (SAM) 3 nm Hafnium Oxide (HfO2) on 2 nm Silicon Dioxide (SiO2) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).
SAM: amine terminated SAM attached to the HfO2 film.
SiO2 thickness: 2 nm nominal blanket with no patterning.
HfO2 thickness: 3 nm nominal blanket with no patterning.

F)  Electron-beam patterned fin structures on 3 nm Hafnium Oxide (HfO2) on 2 nm Silicon Dioxide (SiO2) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).
SiO2 thickness: 2 nm nominal.
HfO2 thickness: 3 nm nominal.
Patterning: e-beam lithography to pattern fin structures with a width of 30 nm, height of 30 nm and length 5 μm (micrometers). Fin topology must conform to properties described in the following report: ACS Nano 12, 6577–6587 (2018) https://doi.org/10.1021/acsnano.8b01339.

NIST conducted market research in February to April 2025 to determine what sources could potentially meet NIST’s minimum requirements. This included searches on GSA; SAM; Thomas Register; Professional journals, surveying vendor websites; speaking with subject matter experts inside and outside of NIST; and issuance of a Sources Sought Notice on SAM.gov. The results of market research revealed that only International Business Machines (IBM) Corporation (UEI: VV9KH3L99VE3) appears to be capable of meeting NIST’s requirements.

However, any sources that believe they are capable of meeting NIST’s minimum requirements are encouraged to respond to this notice by the response date to provide the following information at a minimum: Company Unique Entity Identifier (UEI) number in https://sam.gov; details about what your company is capable of providing that meets or exceeds NIST’s minimum requirements; whether your company is an authorized reseller of the product or service being cited and evidence of such authorization; and any other information that can help NIST determine whether this requirement may be competitively satisfied. 

A determination by the Government not to compete the proposed acquisition based upon responses to this notice is solely within the discretion of the Government. Information received will be considered solely for the purpose of determining whether to conduct a competitive procurement. Only responses received by the offers due date and time of this notice will be considered by the government. Responses shall be submitted via email to nina.lin@nist.gov.

Notice of Intent to Sole Source for Silicon Wafers with Multiple Thin Films

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Notice of Intent to Noncompetitively acquire Semiconductor Wafers with Multiple Thin Films.

This notice is not a request for a quotation. A solicitation document will not be issued, and quotations will not be requested.

This acquisition is being conducted under the authority of FAR 13.106-1(b). The North American Industry Classification System (NAICS) code for this acquisition is 334413, Semiconductor and Related Device Manufacturing which has a small business size standard of 1,250 employees.

The semiconductor supply chain is global, specialized, and interconnected. Chipmakers do business with thousands of individual suppliers that provide the highly complex materials and tools used to produce semiconductors. To address the lack of full visibility into the semiconductors markets supply chain and R&D ecosystem gaps the National Institute of Standards and Technology (NIST) will conduct the measurement science, or metrology, critical to the development of new materials, packaging, and production methods in chip manufacturing. 

With this goal, the NIST Biomedical Measurement Technologies Group within the Microsystems and Nanotechnology Division of the Physical Measurement Laboratory (PML) requires specialized test substrates composed of silicon wafers enhanced with multiple thin films. These substrates are a critical component of a CHIPS program to assess the functionalization of semiconductor substrates with passivation and biorecognition elements to advance measurements of manufacturable CMOS biosensors.

This project aims to rigorously assess the stability and reliability of biomolecule attachment to semiconductor surfaces, which is vital for the development of effective biosensors. The substrates required will serve as an industry reference point for NIST's internal samples. As such, they must be manufactured on high-quality foundry or research-grade semiconductor fabrication lines capable of processing 200 mm silicon wafers. The thin films must be applied either uniformly as a continuous layer over the entire wafer surface or in a precise patterned layout using either optical or e-beam lithography, depending on the specific requirements outlined in the specifications below.

The Contractor shall provide test substrates that meets all technical specifications and performance specifications identified below:
 

A) Patterned films comprising 3 nm Hafnium Oxide (HfO2) on 2 nm Silicon Dioxide (SiO2) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).
SiO2 thickness: 2 nm nominal with structures patterned using optical lithography.
HfO2 thickness: 3 nm nominal with structures patterned using optical lithography.
Patterns: Patterns in the micrometer size either as lines, squares or rectangles defined using optical lithography.


B) Blanket films comprising 3 nm Hafnium Oxide (HfO2) on 2 nm Silicon Dioxide (SiO2) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).
SiO2 thickness: 2 nm nominal blanket with no patterning.
HfO2 thickness: 3 nm nominal blanket with no patterning.


C)  Blanket films comprising 2 nm Silicon Dioxide (SiO2) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).
SiO2 thickness: 2 nm nominal blanket with no patterning.


D)  Blanket films comprising Gold (Au) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).

E) Blanket films comprising amine terminated self-assembled monolayers (SAM) 3 nm Hafnium Oxide (HfO2) on 2 nm Silicon Dioxide (SiO2) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).
SAM: amine terminated SAM attached to the HfO2 film.
SiO2 thickness: 2 nm nominal blanket with no patterning.
HfO2 thickness: 3 nm nominal blanket with no patterning.

F)  Electron-beam patterned fin structures on 3 nm Hafnium Oxide (HfO2) on 2 nm Silicon Dioxide (SiO2) on Silicon wafers.

Substrate: 200 mm diameter Silicon wafer either single side polished or double side polished (preferred).
SiO2 thickness: 2 nm nominal.
HfO2 thickness: 3 nm nominal.
Patterning: e-beam lithography to pattern fin structures with a width of 30 nm, height of 30 nm and length 5 μm (micrometers). Fin topology must conform to properties described in the following report: ACS Nano 12, 6577–6587 (2018) https://doi.org/10.1021/acsnano.8b01339.

NIST conducted market research in February to April 2025 to determine what sources could potentially meet NIST’s minimum requirements. This included searches on GSA; SAM; Thomas Register; Professional journals, surveying vendor websites; speaking with subject matter experts inside and outside of NIST; and issuance of a Sources Sought Notice on SAM.gov. The results of market research revealed that only International Business Machines (IBM) Corporation (UEI: EDHQH5AXXQZ5) appears to be capable of meeting NIST’s requirements.

However, any sources that believe they are capable of meeting NIST’s minimum requirements are encouraged to respond to this notice by the response date to provide the following information at a minimum: Company Unique Entity Identifier (UEI) number in https://sam.gov; details about what your company is capable of providing that meets or exceeds NIST’s minimum requirements; whether your company is an authorized reseller of the product or service being cited and evidence of such authorization; and any other information that can help NIST determine whether this requirement may be competitively satisfied. 

A determination by the Government not to compete the proposed acquisition based upon responses to this notice is solely within the discretion of the Government. Information received will be considered solely for the purpose of determining whether to conduct a competitive procurement. Only responses received by the offers due date and time of this notice will be considered by the government. Responses shall be submitted via email to nina.lin@nist.gov.

Notice of Intent to Sole Source for Silicon Wafers with Multiple Thin Films

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